In the fields of computer science and computing system architecture, FIFO is an acronym for “first in, first out,” which is a common method for organizing and manipulating a data buffer as a queue. In a FIFO implementation, processing of data structures that are input to a data buffer is analogous to servicing a queue on a first-come, first-served (FCFS) basis. That is, the oldest (first) entry into a FIFO buffer is processed first. Communication network bridges, switches, and routers used in computer networks may employ FIFO buffers to temporarily store data structures (referred to as “data packets”) as they await service from limited processing resources that are tasked with facilitating progress of the data packets through a computing architecture. In common computer network architectures, one or more FIFO buffers may be dedicated to service a single network connection. Also, multiple FIFOs may be designed to simultaneously and independently queue different types of information (e.g., data type-specific buffers).
Depending on the application, a FIFO may be implemented as a hardware shift register(s) or in software in a memory structure. The ends of a FIFO queue are often referred to as a head and a tail. As used herein, data structures enter a queue at the tail, and remain in the queue until they reach the head (from which the data structure leaves the queue). That is, the data structure at head of the queue is processed before subsequently-queued data structures.
A FIFO is commonly implemented as a circular queue characterized by two pointers: a Read Pointer/Read Address Register, and a Write Pointer/Write Address Register. In such a buffer implementation, read and write addresses are initially both at a first memory location and the FIFO queue is said to have a state of Empty. When the read address register reaches the write address register, the FIFO may trigger an Empty signal and stall subsequent read requests until data is available. When the write address register reaches the read address register, the FIFO is said to have a state of Full and the FIFO may trigger a Full signal and stall subsequent write requests until space is available.
As related above, microprocessors commonly employ queues to buffer traffic going to or coming from a network. The Air Force Research Laboratory (AFRL) Secure Processor version 2 (SPv2), for example, currently employs incoming and outgoing FIFO buffers for traffic coming from/to a crossbar network switch. Future chip designs may employ additional FIFO buffers to external Analog-to-Digital (A/D) and Digital-to-Analog (D/A) converters. Data from such devices are expected to come at high data rates with minimal framing. Transmitting and consuming/generating such data efficiently poses an architectural challenge.
In some computing system implementations, handling network traffic can tie up the available processor(s) as packets of data are processed. If incoming data packets are sent to the cache to then be written to memory and, eventually, recalled into cache and processed, this may result in significant latency penalties for memory access and susceptibility to pollution of the cache. These latencies, combined with network congestion and overhead of handling network protocols, can result in delays within the data pipeline and can lead to dropped data and/or corrupted data streams. A need exists for a more efficient means to handle queued data packets characterized by high data rates.
This background information is provided to reveal information believed by the applicant to be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present invention.